Integrated Circuits (ICs) typically have clock networks (nets) to distribute one or more clock signals as standard time references to each section of an IC. Different sections of the IC can have significantly different clock loadings and different needs for amplification of the clock signals. These differences between the sections can cause propagation time differences in clock signals, sometimes called clock tree skew, between the sections of the IC.
If the clock tree skew becomes too large between the sections of an IC compared to the clock period, this can become a serious problem in IC design for virtually any type of IC.